/**
 ** 指令缓冲区，可容纳64条指令
**/
module instCache (
    input wire clk,
    input wire [11:0] pc_1, pc_2,
    output reg [31:0] inst_one, inst_two  //每个时钟向外输出两条指令
);
    reg [31:0] insts [0:63];

    initial begin
        //初始化指令
        insts[0] = 32'b00000000000011000000001010000001;
        insts[1] = 32'b00000000000000011100010000000001;
        insts[2] = 32'b00000000000100011001000010000001;
        insts[3] = 32'b00000000000001011100001000000001;
        insts[4] = 32'b00000000000000001010010010000001;
        insts[5] = 32'b00000000000000001100000100000001;
        insts[6] = 32'b00000000000010111110001110000001;
        insts[7] = 32'b00000000000000100000100000000001;
        insts[8] = 32'b00000000000001011100101010000001;
        insts[9] = 32'b00000000000101001001100100000001;
        insts[10] = 32'b00000000000110001000010100000001;
        insts[11] = 32'b00000000000000011111111100000001;
        insts[12] = 32'b00000010100000101000000010110011;
        insts[13] = 32'b00000000010000001000000010110011;
        insts[14] = 32'b00000000010101001000001010110011;
        insts[15] = 32'b00000010010101000000001010110011;
        insts[16] = 32'b00000010001000101000000100110011;
        insts[17] = 32'b00000000100100010000000100110011;
        insts[18] = 32'b00000000000100111000100000110011;
        insts[19] = 32'b00000000000100111000100000110011;
        insts[20] = 32'b00000000000101001000001110110011;
        insts[21] = 32'b00000001001010101000001110110011;
        insts[22] = 32'b00000000011101010000010000110011;
        insts[23] = 32'b00000001111010010000010100110011;
        insts[24] = 32'b00000010100000101000000010110011;
        insts[25] = 32'b00000000010000001000000010110011;
        insts[26] = 32'b00000000010101001000001010110011;
        insts[27] = 32'b00000010010101000000001010110011;
        insts[28] = 32'b00000010001000101000000100110011;
        insts[29] = 32'b00000000100100010000000100110011;
        insts[30] = 32'b00000000000100111000100000110011;
        insts[31] = 32'b00000000000100111000100000110011;
        insts[32] = 32'b00000000000101001000001110110011;
        insts[33] = 32'b00000001001010101000001110110011;
        insts[34] = 32'b00000000011101010000010000110011;
        insts[35] = 32'b00000001111010010000010100110011;
        insts[36] = 32'b00000010100000101000000010110011;
        insts[37] = 32'b00000000010000001000000010110011;
        insts[38] = 32'b00000000010101001000001010110011;
        insts[39] = 32'b00000010010101000000001010110011;
        insts[40] = 32'b00000010001000101000000100110011;
        insts[41] = 32'b00000000100100010000000100110011;
        insts[42] = 32'b00000000000100111000100000110011;
        insts[43] = 32'b00000000000100111000100000110011;
        insts[44] = 32'b00000000000101001000001110110011;
        insts[45] = 32'b00000001001010101000001110110011;
        insts[46] = 32'b00000000011101010000010000110011;
        insts[47] = 32'b00000001111010010000010100110011;
    end

    //每次输出两条指令
    always @(posedge clk) begin
        if (pc_1<48 && pc_2<48) begin
            inst_one <= insts[pc_1];
            inst_two <= insts[pc_2];
        end
        else begin
            inst_one <= 32'h00000000;
            inst_two <= 32'h00000000;
        end
    end
    
endmodule